wv3hg64m32eeu-d4 october 2006 rev. 3 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 256mb ? 64mx32 ddr2 sdram unbuffered description the wv3hg64m32eeu is a 64mx32 double data rate 2 sdram memory module based on 512mb ddr2 sdram components. the module consists of four 64mx8, in fbga package mounted on a 200 pin so-dimm fr4 substrate. * this product is under development, is not quali ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features 200-pin, small-outline dimm (so-dimm) fast data transfer rates: pc2-5300*, pc2-4200 and pc2-3200 utilizes 667*, 533 and 400 mb/s ddr2 sdram components v cc = 1.8v 0.1v v ccspd = 1.7v to 3.6v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture dll to align dq and dqs transitions with ck multiple internal device banks for concurrent operation supports duplicate output strobe (rdqs/rdqs#) programmable cas# latency (cl): 3, 4, and 5 programmable burst: length (4, 8) adjustable data-output drive strength on-die termination (odt) serial presence detect (spd) with eeprom auto & self refresh (64ms: 8,192 cycle refresh) row addr: a0~a13, column addr: a0~a9, bank addr: ba0~ba1 gold edge contacts rohs compliant jedec package option ? 200 pin (so-dimm) ? pcb ? 30.00mm (1.181") typ. operating frequencies pc2-5300* pc2-4200 pc2-3200 clock speed 333mhz 266mhz 200mhz cl-t rcd -t rp 5-5-5 4-4-4 3-3-3 note: ? consult factory for availability
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin names symbol description a0-a13 address input odt0 on-die termination ck0, ck0# differential clock inputs cke0 clock enable input cs0# chip select ras#, cas#, we# command inputs ba0, ba1 bank address inputs dm0-dm3 input data mask a10/ap address input/auto precharge dq0-dq31 data input/output dqs0-dqs3 dqs0#-dqs3# data strobe scl serial clock for presence detect sa0-sa1 presence detect address inputs sda serial presence detect data v cc power supply: +1.8v 0.1v v ref sstl_18 reference voltage v ss ground v ccspd serial eeprom positive power supply nc no connect pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 vref 51 dqs2 101 a1 151 nc 2v ss 52 dm2 102 a0 152 nc 3v ss 53 v ss 103 vcc 153 nc 4 dq4 54 v ss 104 vcc 154 nc 5 dq0 55 dq18 105 a10/ap 155 v ss 6 dq5 56 dq22 106 ba1 156 v ss 7 dq1 57 dq19 107 ba0 157 nc 8v ss 58 dq23 108 ras# 158 nc 9v ss 59 v ss 109 we# 159 nc 10 dm0 60 v ss 110 cs0# 160 nc 11 dqs0# 61 dq24 111 vcc 161 v ss 12 v ss 62 dq28 112 vcc 162 v ss 13 dqs0 63 dq25 113 cas# 163 nc 14 dq6 64 dq29 114 odt0 164 nc 15 v ss 65 v ss 115 nc 165 v ss 16 dq7 66 v ss 116 a13 166 nc 17 dq2 67 dm3 117 vcc 167 nc 18 v ss 68 dqs3# 118 vcc 168 v ss 19 dq3 69 nc 119 nc 169 nc 20 dq12 70 dqs3 120 nc 170 nc 21 v ss 71 v ss 121 v ss 171 v ss 22 dq13 72 v ss 122 v ss 172 v ss 23 dq8 73 dq26 123 nc 173 nc 24 v ss 74 dq30 124 nc 174 nc 25 dq9 75 dq27 125 nc 175 nc 26 dm1 76 dq31 126 nc 176 nc 27 v ss 77 v ss 127 v ss 177 v ss 28 v ss 78 v ss 128 v ss 178 v ss 29 dqs1# 79 cke0 129 nc 179 nc 30 ck0 80 nc 130 nc 180 nc 31 dqs1 81 vcc 131 nc 181 nc 32 ck0# 82 vcc 132 v ss 182 nc 33 v ss 83 nc 133 v ss 183 v ss 34 v ss 84 nc 134 nc 184 v ss 35 dq10 85 nc 135 nc 185 nc 36 dq14 86 nc 136 nc 186 nc 37 dq11 87 vcc 137 nc 187 v ss 38 dq15 88 vcc 138 v ss 188 nc 39 v ss 89 a12 139 v ss 189 nc 40 v ss 90 a11 140 nc 190 v ss 41 v ss 91 a9 141 nc 191 nc 42 v ss 92 a7 142 nc 192 nc 43 dq16 93 a8 143 nc 193 v ss 44 dq20 94 a6 144 v ss 194 nc 45 dq17 95 vcc 145 v ss 195 sda 46 dq21 96 vcc 146 nc 196 v ss 47 v ss 97 a5 147 nc 197 scl 48 v ss 98 a4 148 nc 198 sa0 49 dqs2# 99 a3 149 v ss 199 vccspd 50 nc 100 a2 150 v ss 200 sa1
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs#dqs dqs# dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm cs# dqs dqs# dqs0# dqs0 dm0 cs0# dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 ddr2 sdrams ddr2 sdrams ck0 ck0# 100 a0 serial pd a1 a2 sa0 sa1 sda scl wp ba0-ba1 a0-a13 ras# cas# we# cke0 odt0 note: all resistor value, are 22 ohms 5% unless otherwise specified. ba0-ba1: ddr2 sdrams a0-a13: ddr2 sdrams ras#: ddr2 sdrams cas#: ddr2 sdrams we#: ddr2 sdrams cke0: ddr2 sdrams odt0: ddr2 sdrams v ccspd v cc v ref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams 3 3
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 ? c i l input leakage current; any input 0v wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs input/output capacitance t a = 25c, f = 100mhz parameter symbol min max units input capacitance (a0~a13, ba0~ba1, ras#, cas#, we#) c in1 812pf input capacitance cke0, odt c in2 812pf input capacitance cs0# c in3 812pf input capacitance (ck0, ck0#) c in4 812pf input capacitance (dm0 ~ dm3), (dqs0 ~ dqs3) c in5 (665) 6.5 7.5 pf c in5 (534) 6.5 8 pf input capacitance (dq0 ~ dq31) c out1 (665) 6.5 7.5 pf c out1 (534) 6.5 8 pf notes: ? ac speci cation is based on samsung components. other dram manufactures speci cation may be different. operating temperature condition parameter symbol rating units notes operating temperature (commercial) toper 0 to 85 c 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jeded jesd51.2 2. at 0c - 85c, operation temperature range, all dram speci cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih (dc) v ref + 0.125 v cc + 0.300 v input low (logic 0) voltage v il (dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage ddr2-400 & ddr2-533 v ih (ac) v ref + 0.250 - v input low (logic 1) voltage ddr2-667 v ih (ac) v ref + 0.200 - v input low (logic 0) voltage ddr2-400 & ddr2-533 v il (ac) - v ref - 0.250 v input low (logic 0) voltage ddr2-667 v il (ac) - v ref - 0.200 v
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs i cc specification v cc = +1.8v 0.1v symbol proposed conditions 665 534 403 units i cc0* operating one bank active-precharge; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching 340 320 320 ma i cc1* operating one bank active-read-precharge; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w 400 380 380 ma i cc2p** precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating 32 32 32 ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating 140 120 120 ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are switching 160 140 140 ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 120 120 120 ma slow pdn exit mrs(12) = 1 48 48 48 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t rc = t rc (i cc, t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching 220 200 200 ma i cc4w* operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching 560 480 440 ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w 580 500 440 ma i cc5** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching 600 560 560 ma i cc6** self refresh current; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal 32 32 32 ma i cc7* operating bank interleave read current; all bank interlea vin g reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching. 880 880 880 ma i cc speci cation is based on samsung components. other dram manufactures speci cation may be different. note: *: value calculated as one module rank in this operating condition, and all other module ranks in i cc2p (cke low) mode. **: value calculated re ects all module ranks in this operating condition.
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 sdram component ac timing parameters & specifications ac characteristics 665 534 403 parameter symbol min max min max min max unit clock clock cycle time cl = 5 t ck (5) 3,000 8,000 ps cl = 4 t ck (4) 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps clock jitter t j i t -125 125 -125 125 -125 125 ps data dq output access time from ck/ck# t ac -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz t ac max t ac max t ac max ps data-out low-impedance window from ck/ck# t lz t ac min t ac max t ac min t ac max t ac min t ac max ps dq and dm input setup time relative to dqs t ds 100 100 150 ps dq and dm input hold time relative to dqs t dh 225 225 275 ps dq and dm input pulse width (for each input) t d i pw 0.35 0.35 0.35 t ck data hold skew factor t qhs 340 400 450 ps dq?dqs hold, dqs to rst dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising ? setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 240 300 350 ps dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres 000p s dqs write preamble t wpre 0.35 0.35 0.35 t ck dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to rst dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck address and control input pulse width for each input t ipw 0.6 0.6 0.6 t ck address and control input setup time t is 200 250 350 ps address and control input hold time t ih 275 375 475 ps address and control input hold time t ccd 222t ck note: ac speci cation is based on samsung components. other dram manufactures speci cation may be different. continued on next page
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 sdram component ac timing parameters & specifications (cont'd) ac characteristics 665 534 403 parameter symbol min max min max min max unit command and address active to active (same bank) command t rc 55 60 65 ns active bank a to active bank b command t rrd 7.5 7.5 7.5 ns active to read or write delay t rcd 15 15 15 ns four bank activate period t faw 37.5 37.5 37.5 37.5 37.5 37.5 ns active to precharge command t ras 45 70,000 45 70,000 45 70,000 ns internal read to precharge command delay t rtp 7.5 7.5 7.5 ns write recovery time t wr 15 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp t wr + t rp ns internal write to read command delay t wtr 7.5 7.5 10 ns precharge command period t rp 15 15 15 ns precharge all command period t rpa t rp+ t ck t rp+ t ck t rp+ t ck ns load mode command cycle time t mrd 222t ck cke low to ck,ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns self refresh refresh to active of refresh to refresh command interval t rfc 105 70,000 105 70,000 105 70,000 ns average periodic refresh interval t ref i 7.8 7.8 7.8 s exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 200 t ck exit self refresh timing reference ti sxr t is t is t is ps odt odt turn-on delay t aond 222222t ck odt turn-on t aon t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 ps odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 ps odt to power-down entry latency t anpd 333t ck odt power-down exit latency t axpd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard 222t ck exit active power-down to read command, mr[bit12=1] t xards 7 - al 6 - al 6 - al t ck a exit precharge power-down to any non-read command. t xp 222t ck cke minimum high/low time t cke 333t ck note: ac speci cation is based on samsung components. other dram manufactures speci cation may be different.
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.80 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ pin 199 pin 200 pin 2 2.15 (0.085) 6.00 (0.236) 63.60 (2.504) 2.55 (0.100) 1.00 (0.039) typ typ back view front view 30.15 (1.187) 29.85 (1.175) 47.40 (1.866) typ 11.40 (0.449) typ 4.2 (0.165) typ 4.10(0.161) (2x) 3.90(0.154) package dimensions for d4 ** all dimensions are in millimeters and (inches) ordering information for d4 part number clock/data rate frequency cas latency t rcd t rp height** wv3hg64m32eeu665d4xxg* 333mhz/667mb/s 5 5 5 30.00mm (1.181") typ wv3hg64m32eeu534d4xxg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ wv3hg64m32eeu403d4xxg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ * consult factory for availability notes: ? rohs product. ("g" = rohs compliant) ? vendor speci c part numbers are used to provide memory components source control. the place holder for this is shown as lower case ?x? in t he part numbers above and is to be replaced with the respective vendors code. consult factory for quali ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 h g 64m 32 e e u xxx d4 x x g wedc memory (sdram) ddr 2 gold depth bus width component width x8 1.8v unbuffered speed (mb/s) package 200 pin industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) g = rohs compliant
wv3hg64m32eeu-d4 october 2006 rev. 3 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 256mb ? 64mx32 ddr2 sdram unbuffered dram die options: ? samsung: c-die, will move to e-die q2'06 ? micron: u37y: b-die revision history rev # history release date status rev 0 created 3-06 advanced rev 1 1.1 added row, column, and bank address 3-23-06 advanced rev 2 2.1 correction on component used, (512mb) 2.2 added v ccq update 2.3 added "x" to part number to indicate industrial temp option 2.4 added "x" to part numbering guide to indicate industrial temp option 2.5 added die rev info 5-06 advanced rev 3 3.1 updated ac title to indicate component ac specs only 10-06 advanced
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